1. Field of the Invention
The invention relates to semiconductor processing. More specifically, the invention relates to integration of a thin-film resistor in a wiring level.
2. Background of the Invention
Metal resistors integrated in the back-end-of-line (BEOL) are critical for radio frequency (RF) circuits requiring small resistance tolerances and low parasitic capacitance. Tantalum nitride (TaN) is commonly used as a thin-film resistor in copper (Cu) BEOL technology since TaN thin films can be relatively easily integrated in the Cu BEOL. Cu interconnects are formed by damascene processes known in the art including forming a trough in a dielectric layer (i.e. silicon oxide), forming a layer of Cu in the trough, and chemical-mechanical polishing (CMP) to remove excess Cu from the dielectric layer. Thin-film resistors can be formed immediately after the CMP step since a planar surface is provided for the thin-film resistor to be formed upon. Also, the thin-film resistor is typically formed in close proximity to an interconnect so the same via can be used to contact both the thin-film resistor and the interconnect. Thus, conventional process integration adds only one photolithographic masking step to form the thin-film resistor in Cu BEOL.
In aluminum BEOL technology, a subtractive etch process is typically used to form aluminum interconnects in a wiring level on a semiconductor substrate. A layer of aluminum is formed on an upper surface of a dielectric layer such as, silicon oxide, and is patterned by a photolithographic process. Exposed aluminum is removed by an etch process such as reactive ion etching to form aluminum interconnects on the upper surface of the dielectric layer. The formation of aluminum interconnects by a subtractive etch process results in topography in the wiring level.
To obtain a planar surface on an aluminum wiring level, a second dielectric layer is formed over the aluminum interconnects and planarized to form a planar surface. Another requirement for the thin-film resistor is that the resistor should be in close proximity to an interconnect to allow the use of the same via for both the resistor and the interconnect. The thickness of the second dielectric layer required to form a planar surface results in the thin-film resistor being located a relatively large distance from an interconnect such that a common via cannot be used for both the thin-film resistor and the interconnect.
Thus, the topography associated with a wiring level in aluminum BEOL technology increases the process complexity and costs required to integrate a thin-film resistor.